
Micrel, Inc.
KSZ8842-PMQL/PMBL
October 2007
97
M9999-100207-1.5
Host VID Control Register (Offset 0x0544): P3VIDCR
This register contains the global per port control for the switch host port function.
Bit
Default
R/W
Description
15-13
000
RW
User Priority bits
Host Port default tag bits [15-13] for user priority
12
0
RW
CFI bit
Host Port default tag bit 12 for CFI
11-0
0x001
RW
VID bits
Host Port default tag bits [11-0] for VID
Note: P3VIDCR serve two purposes:
(1) Associated with the ingress untagged packets, and used for egress tagging.
(2) Default VID for the ingress untagged or null-VID-tagged packets, and used for address look up.
Host Control Register 3 (Offset 0x0546): P3CR3
This register contains the host port control register for the switch host port function.
Bit
Default
Name
R/W
Description
15 – 5
000
Reserved
RO
Reserved
4
0
Reserved
3-2
00
0
RW
Ingress Limit Mode
These bits determine what kinds of frames are limited and
counted against Ingress limiting as follows:
00 = Limit and count all frames
01 = Limit and count Broadcast, Multicast, and flooded
unicast frames
10 = Limit and count Broadcast and Multicast frames only
11 = Limit and count Broadcast frames only
1
0
RW
Count IFG bytes
1 = each frame’s minimum inter frame gap (IFG) bytes (12
per frame) are included in Ingress and Egress rate limiting
calculations.
0 = IFG bytes are not counted
0
RW
Count Preamble bytes
1 = each frame’s preamble bytes (8 per frame) are included
in Ingress and Egress rate limiting calculations.
0 = preamble bytes are not counted